The 2nm project that builds no chip

This project builds no chip. Its scope stops at three things: AI models, the optimisation that moves those models onto inference silicon, and validation of usefulness in a hospital — the development of the semiconductor device itself is not included. The more than ¥6bn spent before the stage gate buys a requirements specification written in measured clinical data, and a review in March 2029. As for the 2nm chip in the title: it is envisaged as designed by IBM, its manufacturer is undecided — and for the project's first two and a half years, it will not exist as hardware.

In a hospital, the GPU hits three walls

Start with the problem. CT, MRI, ultrasound and surgical microscopes produce ever higher-resolution images, and the data swells with them — above all photon-counting CT, the next-generation scanner that counts individual X-ray photons and measures their energy, and the subject of this project's first system. The briefing's figures: resolution can rise to about four times the conventional level, and material-decomposition information multiplies the data volume a further three to five times. The natural tool for such data is a GPU, but a high-performance GPU draws 300–700 watts. In a data centre that is unremarkable. In a machine that must fit an examination room or be wheeled to an operating table, heat, volume and power supply are hard constraints.

The second wall is where the data sits. Patient information is sensitive; processing it in an outside cloud is awkward on bandwidth, latency and compliance. The project's own phrasing is "hard to send out", not "cannot be sent out" — the distinction matters. The third wall has a concrete shape. Clinical work runs trained models for inference — judging "what is this" — and does not need everything a general-purpose GPU carries for large-scale training. What it needs is the answer immediately. A current GPU running several AI processes at once over 4K surgical video falls to 1–2 frames a second (briefing figure).

That is why the technical choice is written into the theme's name from the start: inference-specific. Not a general compute giant, but a chip that only infers — fast, and cool enough to live inside the equipment.

Three systems, three rooms

Real-time image diagnosis support (Hokkaido University + Fujifilm). High-speed reconstruction AI and organ-segmentation AI for photon-counting CT: reconstruction from 5 slices a second to 25; segmentation of some 1,000 anatomical classes across the body from about 25 seconds to within 5, supporting radiologists' reading and reporting. Fujifilm's aim goes beyond the AI — system development aimed at CT scanners, PACS (imaging systems) and reading terminals (press release). The chip, in other words, is a ticket in; the product is the workflow of the whole device.

Real-time clinical support (Hokkaido University + GE HealthCare). Live ultrasound images overlaid in real time on previously acquired CT or MRI scans, continuously correcting for organs that move and deform with breathing, at a target of 15 frames a second. The envisaged settings are heat ablation of liver tumours and needle biopsies (briefing).

Real-time surgical support (Hokkaido University, with imec supporting). Building on the university's existing neurosurgical video AI, three processes — instrument tracking, anatomical-structure recognition, bleeding detection — are integrated into a small "AI Box" that can sit in an operating room: from the current 1–2 frames a second at 4K to 30. imec's part is to convert the models, quantise them, and integrate them into the inference chip's pipeline.

All three systems share one foundation: an inference platform running in real time inside the machine, at the edge.

Homework first, chip later

The most instructive thing about this project is its sequence. In the first phase, up to the stage gate in March 2029, model training and algorithm development proceed in a GPU environment while inference runs on IBM's Spyre — an accelerator fabricated by Samsung on 5nm, chosen because its development environment and architecture have high affinity with the envisaged 2nm chip (briefing). Two deliverables are due before the gate: the three systems implemented, functionally verified and optimised on Spyre; and a quantitative forecast — grounded in measured values, showing that migrating to 2nm can reach at least 5x image-processing speed and 10x energy efficiency. Only after passing the gate does the project move to validation on actual 2nm silicon, with clinical usefulness verified at Hokkaido University Hospital, concluding in September 2031.

Rapidus's 2nm mass-production target (second half of 2027, Reuters) is a condition outside the project, not a project milestone. Device certification is sought only after the project ends; market launch follows it.

Which is to say: for at least two and a half years, "2nm medical AI" runs on a 5nm chip made by Samsung. And on who would make the 2nm chip, the sources differ audibly in temperature:

Fact

Nikkei (20 Oct 2026): Professor Kudo told a press conference the "leading candidate is Rapidus". TECH+, from the briefing: LSTC hopes to adopt a domestic semiconductor, Rapidus manufacturing is "one of the candidates"; the 2nm chip is envisaged as designed by IBM, but neither designer nor manufacturer is fixed. Reuters (20 Oct 2026): the chip is envisaged as produced by Rapidus under IBM licence. The three accounts share one point — none of them says "decided".

Chairman Higashi's remark at the launch points at why the sequence is deliberate: the project exists to "bring together the expertise of semiconductors, AI and medical devices, and connect leading-edge semiconductors to technology that is genuinely useful in clinical settings" (Nikkei). Chip and application developed at the same time is this project's design, not its accident.

Can it be done: item by item

A declaration first: everything in this section is this publication's editorial judgement — not measurement, not statistics, but the direction we are willing to bet on with the known facts laid out. Split "can it be done" apart, and there is more than one answer:

The three AI systems landing before the gate (on Spyre-class hardware) — likely. In substance this is software engineering: Fujifilm has REiLI deployment experience, the university has a clinical site and an existing surgical-video AI, and there are two and a half years to the gate. This segment has nothing to do with 2nm — which is exactly why it is the most solid.

The quantitative forecast passing the gate — possible, but discount it. Tenfold efficiency for a fixed-task inference chip against a general-purpose GPU is not unusual. But the baseline is "commercial GPUs in current medical equipment", and that baseline moves as GPUs improve; and "image-processing speed" is an end-to-end metric (reconstruction included), harder than a chip benchmark. However solid the forecast, it remains a forecast — which is what the gate exists to examine.

Switching to actual 2nm silicon on schedule after the gate — fifty-fifty, shading risky. It requires three things outside the project to hold at once: IBM's design maturing on time, a manufacturer (still undecided) delivering on time, and clinical validation at the university hospital not slipping. The two-phase design with a gate is precisely a hedge against this segment: before the gate, finish everything that can be controlled.

Certification and launch — not on the project's clock. Certification of a medical device carrying the 2nm chip is to be obtained after the project ends in September 2031, with market launch after that (certification of the AI software proceeds in parallel during the project). Anyone reading 2031 as a "product launch year" has misread it.

One more thing should be said plainly: medical inference chips are a small-volume market, and this project will not fill any factory. What it produces is a specification, a method, and a clinical data pipeline.

Judgement

Our reading

What this project delivers is not a chip but a sequence — let hospitals run their needs into measured data on somebody else's chip first, then let that data define the 2nm chip that does not yet exist; the more than ¥6bn buys exactly that specification and the March 2029 review. One physical fact carries the sequence: the GPU fails to enter the equipment not for lack of compute, but because 300–700 watts is too hot and too big — the contest is decided in watts, not peak compute. The hospital is only the first room; TECH+ notes the model-porting method is expected to extend to manufacturing, robotics and other edge settings. The risk is printed on the same page: if the March 2029 forecast fails the gate, or if design and manufacturing stay undecided after it, "application first" becomes "application idling" — systems perfected on Spyre would prove nothing about domestic 2nm. Watch the gate in March 2029, and the silicon by September 2031. Those two dates are this article's shelf life.

What each side wants

A project gets adopted for more than technical merit. Lay out each party's motive, and the project's shape becomes clear.

The state (METI and NEDO) wants a use case, and says so. The first two steps of Japan's semiconductor policy were capacity and factories; the third must answer "who is it for?" The press release is unembarrassed: the aim is to create a social-implementation use case for Japan's domestically produced leading-edge semiconductors. In the same week, under the same programme, a photonics-electronics xPU theme by PFN and America's Tenstorrent was also selected — a portfolio for finding work for domestic chips, not an isolated project. And the day before the announcement (19 October), METI had just put forward a plan for ¥400bn of additional industrial investment in Rapidus over FY2027–29 (still at the request stage, each year subject to approval; if fully executed, cumulative state investment reaches ¥650bn, alongside ¥2tn of private financing still at letter-of-intent stage). Factories need demand stories if the money is to keep making sense.

LSTC and Tetsuro Higashi want the connection; the output is a specification. The same man chairs Rapidus and LSTC: on one side, the factory that will one day make chips; on the other, the association that organises demand. It is not a coincidence, it is institutional design. Higashi said as much at the briefing: leading-edge semiconductors and their applications must be developed at the same time. LSTC's product in this project is not a chip. It is the table at which clinical needs get translated into a chip specification, and the measured data accumulated before the gate.

Fujifilm wants a differentiating vehicle. In December 2019 it announced the acquisition of Hitachi's diagnostic-imaging business for about ¥179bn, completed in March 2021, bringing the full CT, MRI and ultrasound line-up and its channels. But imaging hardware keeps commoditising; the profit sits in software and workflow. Its medical-AI platform REiLI needs a reason to be built into its own machines, and the release states its agenda plainly: system development aimed at CT scanners, PACS and reading terminals — the reconstruction AI for the next generation of machines is already on its own list.

GE HealthCare wants to hold its home ground in ultrasound. Fusion imaging — ultrasound overlaid with CT/MRI — is a clinical feature every maker is contesting; GE HealthCare has development, manufacturing and sales in Japan (headquarters in Hino); the system it carries in this project is precisely that fusion imaging.

Hokkaido University and Hokkaido want a validation site and regional medicine. The release names upgrading regional medical diagnosis as one aim; and Hokkaido is also home to Rapidus's Chitose plant — semiconductors and medicine endorsing each other in the same prefecture.

imec's part is the method itself. Its assignment in this project is specific: convert the surgical AI models, quantise them, integrate the inference pipeline and deploy them onto inference-specific silicon — with the optimisation methods to be extended to the other two systems (TECH+). That is imec's trade: the release's own profile notes that through IC-Link it delivers customised semiconductor solutions from concept to full-scale manufacturing.

IBM is present at both ends. Before the gate, Spyre is the interim hardware; after it, the envisaged 2nm chip is assumed to be IBM-designed. Whoever ends up manufacturing it, IBM's architecture and toolchain are written into the specification first.